“The traditional frequency measurement method has great limitations in practical application. The measurement accuracy of the frequency meter based on the traditional frequency measurement principle will change with the change of the measured signal frequency. The measurement accuracy of the traditional direct frequency measurement method will vary with the As the frequency of the measured signal decreases, the measurement accuracy of the cycle measurement method will decrease with the increase of the frequency of the measured signal. In this paper, a design of a digital frequency meter based on ARM and CPLD broadband is proposed. The microcontroller STM32 is used as the core control chip, and the CPLD programmable logic device is used to realize the equal-precision frequency measurement of the gate measurement technology.
The traditional frequency measurement method has great limitations in practical application. The measurement accuracy of the frequency meter based on the traditional frequency measurement principle will change with the change of the measured signal frequency. The measurement accuracy of the traditional direct frequency measurement method will vary with the As the frequency of the measured signal decreases, the measurement accuracy of the cycle measurement method will decrease with the increase of the frequency of the measured signal. In this paper, a design of a digital frequency meter based on ARM and CPLD broadband is proposed. The microcontroller STM32 is used as the core control chip, and the CPLD programmable logic device is used to realize the equal-precision frequency measurement of the gate measurement technology.
Technical indicators of this design:
Frequency measurement range: 1Hz ~ 200MHz, the resolution is 0.1Hz, the relative error of frequency measurement is one millionth.
Period measurement: The signal measurement range and accuracy requirements are the same as the frequency measurement function.
Duty cycle measurement: 99% accuracy.
Counting range: 0～1000000000, can be paused and reset manually.
Power consumption: 5V×250mA= 1.25W.
The principle of equal precision frequency measurement
The commonly used direct frequency measurement methods mainly include frequency measurement method and period measurement method. The frequency measurement method is to record the number of change cycles (or pulses) Nx of the measured signal within the determined gate time Tw, then the frequency of the measured signal is: fx=Nx/Tw. The measurement cycle method requires the frequency fs of the standard signal. In one cycle Tx of the signal to be measured, the number of cycles Ns of the standard frequency is recorded, then the frequency of the signal to be measured is: fx=fs/Ns. The count value of these two methods will produce ±1 word error, and the test accuracy is related to the value Nx or Ns recorded in the counter. In order to ensure the test accuracy, the period measurement method is generally used for low-frequency signals, and the frequency measurement method is used for high-frequency signals. But because the test is very inconvenient, an equal-accuracy frequency measurement method is proposed. The equal-precision frequency measurement method is developed on the basis of the direct frequency measurement method. Its gate time is not a fixed value, but an integer multiple of the measured signal period, that is, it is synchronized with the measured signal. The control sequence diagram of the equal-precision frequency measurement system is shown in Figure 1.
Fig. 1 Control sequence diagram of equal-precision frequency measurement system
During the measurement process, there are two counters to count the standard signal and the measured signal at the same time. First, the gate opening signal (preset gate rising edge) is given. At this time, the counter does not start counting, but only when the rising edge of the measured signal arrives, the counter really starts counting. Then, when the preset gate closing signal (falling edge) arrives, the counter does not stop counting immediately, but waits until the rising edge of the measured number arrives to end the counting and completes a measurement process. It can be seen that the actual gate time r is not strictly equal to the preset gate time r1, but the difference does not exceed one cycle of the measured signal. Assuming that in an actual gate time r, the count value of the counter for the measured signal is Nx, the count value for the standard signal is Ns, and the frequency of the standard signal is fs, then the frequency of the measured signal is shown in formula (1).
The frequency of the signal under test
Figure 2 is a logic block diagram of equal-precision frequency measurement. CNT1 and CNT2 are two controllable counters. The standard frequency signal fs is input from the clock input terminal CLK of CNT1, and the shaped measured signal fx is input from the clock input terminal CLK of CNT2. . The CEN input terminal in each counter is the clock enable terminal, which controls the clock input. When the preset gate signal is high (preset time starts), the rising edge of the signal under test passes through the output of the D flip-flop, and starts two counters at the same time; similarly, when the preset gate signal is low ( When the preset time expires), the rising edge of the measured signal passes through the output terminal of the D flip-flop, and the counting of the counter is turned off at the same time.
Figure 2 Logic block diagram of equal precision frequency measurement
System Hardware Design
Using ST company’s 32bit processor STM32F103C8 as the main control chip and high reliability programmable logic device EPM240T100C5 combined to design a frequency meter.
The functional characteristics of STM32F103C8 are as follows: (1) The highest frequency can reach 72MHz, with 128/64KB FLASH, 1.25DMIPS/MHz, and it can access the memory with 0 waiting period. (2) The power supply voltage range is 2.0~3.6V. The 8MHz high-speed crystal oscillator is embedded, and the external clock can also be supplied. This system adopts the CPLD clock frequency division supply. (3) The download mode can use the serial wire debugging (SWD) interface and the JTAG interface. The system uses the JTAG download interface.
The functional characteristics of EPM240T100C5 are as follows: (1) It supports the internal clock frequency of 300MHz, and the system uses an active crystal oscillator of 50MHz to supply. (2) The on-chip voltage regulator supports 3.3V, 2.5V or 1.8V power input, and this system uses 3.3V voltage supply. (3) The download mode uses the 10-pin JTAG interface.
1 System hardware structure block diagram
The system controls the internal logic unit by controlling the STM32F103C8 microcontroller and sending data and commands to the CPLD chip EPM240T100 via the SPI bus. EPM240T100 uses an external active crystal oscillator 50MHz to supply, divided by 4 and 12.5MHz as the input clock of the CPU. The hardware structure of the system is shown in Figure 3. It includes a main control chip module, a JTAG download module, a reset circuit module, a host computer Display module, and a measured input module.
Figure 3 System block diagram
2 Digital circuit design of the system
The principle of the microcontroller is shown in Figure 4.The processor of this system uses STM2F103C8, the clock is supplied to the CPU by the CPLD frequency division, the data and commands are transmitted to the CPLD through SPI, and then sent to the host computer through the serial port RS232 for display
Figure 4 Schematic diagram of microcontroller