Almost all electronics designers and embedded system developers have heard of Field Programmable Gate Arrays (FPGAs). With an actual FPGA device, designers and developers know that it has a programmable fabric that can be configured to perform the desired function, but their knowledge may be limited there. Likewise, when it comes to creating a design that can be implemented on an FPGA, they may have heard terms like hardware description language (HDL) and register translation level circuit (RTL), but may not fully understand what they mean.
Similar to Verilog or VHDL, HDL enables FPGA designers to describe design intent just as software developers use programming languages such as C or C++. One of the ways to understand HDL is that it can be used to describe things that happen at the same time, which is how hardware works in the real world. By contrast, software programming languages are often used to describe things that happen sequentially.
Meanwhile, RTL is an abstraction-level circuit commonly used for logic synthesis engine input. The tool translates RTL into logic elements and interconnect networks, which are then implemented within the programmable logic of the FPGA. A logic synthesis engine can be likened to a software developer’s compiler, which takes a high-level program as input and converts it into machine code that is executed by the processor.
The programmable fabric of FPGAs can be used to build hardware accelerators that perform data processing tasks with low power consumption. The programmable fabric can be configured to create one or more soft-core processors better suited for decision-making tasks, and these processors can also control hardware accelerators, including feeding them data and taking action based on the results.
One such processor is RISC-V, an open-source instruction set architecture (ISA) that is freely available through an open-source license. The creators of the RISC-V open source hardware concept were inspired by the success of Linux open source software. One of the great advantages of RISC-V is excellent software compatibility across various design implementations, and the use of these processors has grown dramatically today.
However, the problem for non-FPGA designers who want to use such processors is their lack of expertise in FPGA design languages, tools, and flows. To address this, Lattice semiconductor, a leading supplier of low-power programmable FPGAs, has developed a tool called Lattice Propel™, a graphical user interface (GUI)-based design environment that allows any user, with or without FPGA expertise) can use it to quickly design RISC-V processor-based systems in a drag-and-drop fashion.
The output of Propel is an RTL file that can be sent to the synthesis engine to generate a configuration file that can be loaded into the FPGA. Software developers can then run their RISC-V executables on the FPGA-based RISC-V design implementation, just as they would on any other RISC-V processor. Lattice provides RISC-V IP cores free of charge to its FPGA customers.
Data processing requires a suitable computing engine. Developers have many different options, including devices such as microprocessors (MPUs), microcontrollers (MCUs), graphics processing units (GPUs), FPGAs, and SoCs.
MPUs and MCUs are very efficient when performing decision-making tasks, but when implementing raw data processing algorithms, neither processing time nor power consumption is ideal. SoC can achieve the highest performance with the lowest power consumption, but the disadvantage is that it is expensive, resource-intensive and time-consuming to develop, and the algorithms implemented in such chip architectures are basically fixed and cannot be changed, and the protocols used by the system and standards are constantly changing, so that can create a lot of problems.
Certain data processing tasks, including many AI/ML algorithms, are well suited for parallel processing. The FPGA’s programmable architecture (Figure 1a) can be configured to implement hardware accelerator (HA) functions to execute tasks in a massively parallel manner (Figure 1b), resulting in significantly improved performance while reducing power consumption.
Data co-processing capabilities are also required in many cases, using central processing units (CPUs) to enhance hardware accelerators that can perform advanced decision-making and control functions. Unlike a hard CPU, which is implemented directly in the chip, the programmable architecture of an FPGA enables the implementation of a soft CPU along with the associated bus structures (address, data, control) and any desired peripheral IP functions (Figure 1c).
Figure 1. The structured bus approach is applicable to a wide variety of applications, including embedded vision, security, and artificial intelligence.
It should be noted that additional programmable logic functions and peripheral communication functions (such as USB, MIPI, I2C, SPI, CAN, and UART) can be implemented with hard and/or soft cores, depending on the FPGA device and user requirements. The article is limited in space and will not be repeated here.
Using a soft-core CPU has many advantages, including the ability to configure the processor’s operation and many optional features, such as a dynamic memory access (DMA) controller, to fine-tune it to efficiently meet the requirements of the target application. In addition, the programmable fabric can be configured to implement other peripheral IP functions if desired. As in artificial intelligence applications, programmable logic resources can be used to create simple artificial neural networks for tasks such as inference.
As mentioned earlier, RISC-V is an open source instruction set architecture based on established Reduced Instruction Set Computer (RISC) principles and is available through an open source license. In addition, many companies currently offer RISC-V hardcore or open source operating systems that support RISC-V, and several mainstream software toolchains support this instruction set.
The modular design of RISC-V includes the basic instruction set and other extended instruction sets. Both have grown considerably thanks to the joint efforts of industry, technology and educational institutions. The underlying instruction set specifies instructions (and their encodings), control flow, registers (and their sizes), memory and addressing, logical (ie, integer) operations, and auxiliary functions. A general-purpose computer with full software support, including a general-purpose compiler, can be implemented with just the base instruction set.
Additional functionality can also be implemented through an optional extended instruction set, giving designers the flexibility to choose the functionality required for their application. RISC-V defines a number of extended instruction sets, including A (atomic), F (single-precision floating-point), D (double-precision floating-point), Q (quad-precision floating-point), and C (packed 16-bit instructions to reduce code dimensions, for systems with limited storage space). The above instruction sets can be flexibly selected.
Figure 2. Lattice is the first Flash- and SRAM-based FPGA supplier to support RISC-V.
The huge advantage that FPGA-based soft RISC-V has over hard-core implementations as dedicated processors lies in the huge potential of FPGA reconfigurability to meet various scaling needs.
The Lattice RISC-V Soft IP Kit features a 32-bit RISC-V processor core and optional timer and Programmable Interrupt Controller (PIC) submodules. The CPU core supports the RV32I instruction set, external interrupts, and debugging in accordance with the JTAG IEEE 1149.1 specification.
The timer submodule is a 64-bit real-time counter that compares a real-time register with another register to trigger a timer interrupt. The PIC submodule aggregates up to eight external interrupt inputs into one external interrupt. The processor core accesses the submodule registers by using the industry standard 32-bit AHB-L bus interface.
Designers of many embedded systems are interested in using FPGAs, but are daunted by the thought of using traditional FPGA design tools and HDLs. To address this, Lattice Propel employs a graphical user interface (GUI)-based design environment that allows any user (with or without FPGA expertise) to quickly build and configure RISC-V-based designs using its drag-and-drop design approach processor design.
What Propel outputs is an RTL file in Verilog HDL that can be sent to the synthesis engine to generate a configuration file that can be loaded into the FPGA. This profile is available for the Lattice CrossLink™-NX (for embedded vision applications), Certus™-NX (general purpose FPGA) and MachXO3D™ and Mach™-NX FPGA (safety system control) families of products. Once the FPGA is configured, software developers can run their RISC-V executables on the FPGA-based implementation of RISC-V designs just as they would on any other RISC-V processor.
Lattice Propel consists of two parts. The first is Propel Builder, which provides a graphical drag-and-drop interface that lets users select IP blocks and wire them together. These IP blocks include RISC-V processors (with optional timer and interrupt controllers), AMBA bus structures, interfaces, memory, input/output (I/O), and more. Users can also easily upgrade existing IP modules and obtain new IP modules online.
Figure 3. The Propel interface is intuitive, easy to use, and powerful.
In addition to drag-and-drop IP instantiation, Propel Builder also automates pin connections, wizard-based configuration and parameter settings, and IP integration with step-by-construction corrections.
Next is the Lattice Propel SDK (Software Development Kit), which provides a seamless software development environment. It has an industry standard Integrated Development Environment (IDE) and toolchain. The SDK also provides software/hardware debugging capabilities as well as software libraries and board support packages (BSPs) for Propel Builder-defined systems.
The important thing to note is that Propel works well with downstream tools, and it’s also a standalone program that’s only 0.5 GB in size, making it quick and easy to download and install. Also of interest is that all of Propel’s commands can be written in Tcl, increasing design efficiency and quickly integrating it into the user’s own design environment.
Figure 4. Whether it’s a simple “Hello World” application or a complex embedded control and data processing system, Propel allows users to quickly complete designs
For hardware design, Propel is ideal for teams that need the benefits of FPGAs but lack experience with FPGA hardware design. Additionally, if team members do have experience with FPGA design, they can have more precise control over the design as needed. For software design, Propel provides an industry standard C/C++ development environment. Software developers seem to be using off-the-shelf microcontrollers more.
Designers can use Propel to quickly and easily generate RISC-V soft core-based processor systems in CrossLink-NX, Certus-NX, and Mach-NX FPGAs, providing complex video processing, system control, and system safety functions that Latency is much lower than designs implemented with external stand-alone processors.
In addition to having logic functions and hardware accelerators that perform high-performance data processing tasks at low power consumption, the programmable fabric inside an FPGA can be used to implement one or more soft-core processors better suited for decision-making tasks, as well as hardware accelerators such as control functions such as providing them with data and taking action based on the results.
One such processor is RISC-V, an open-source instruction set architecture (ISA) that is freely available through an open-source license. Lattice is the first Flash- and SRAM-based FPGA vendor to support RISC-V and to offer RISC-V IP cores free of charge to its FPGA customers.
The problem for non-FPGA designers who want to use such processors is their lack of expertise in FPGA design languages, tools, and processes. To address this, Lattice offers Propel to simplify the design process, allowing developers to rapidly design systems based on RISC-V processors.